The present invention relates generally to a digital solid state memories. In particular, the present invention relates to a method and apparatus for control calibration of multiple memory modules within a memory channel.
In a memory subsystem that operates in a source synchronous manner, the device which transmits a data signal on a conductive data line also transmits a strobe signal on a separate conductive line. A pulse in the strobe signal has a predefined phase relationship to each associated pulse in a number of data signals. The pulse in the strobe signal is used to capture bit values in the data signals at the receiving device. This is done by running the data and strobe signals through receiver circuitry which detects the logic levels that are being asserted, and translates them into voltage levels that are suitable for processing by controller circuitry in an integrated circuit (IC) die. The outputs of the receiver circuitry are then fed to a number of latches each of which captures a bit value in a respective data signal in response to a pulse in the strobe signal.
According to certain high speed signaling requirements, the strobe receiver circuit at its front end should have a two input comparator, where each input is terminated at the same termination voltage, which may be half-way between a logic xe2x80x980xe2x80x99 voltage and a logic xe2x80x981xe2x80x99 voltage. The strobe line coming from the memory device is shorted to one of the inputs. The comparator""s output at any time indicates the logic state being detected on the strobe line, as either xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 depending upon whether the strobe signal is being asserted or deasserted by the memory device. The output of the comparator directly feeds the clock input of a latch. A data input of the latch receives a level-translated version of the data signal. The latch thus captures a bit value in the data signal upon every low/high to high/low transition of the comparator output. In other words, the latched bit values are always dictated by the strobe signal. The latter is also referred to here as xe2x80x98continuously forwardingxe2x80x99 the strobe signal.
In some high speed memory specifications such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), as defined by the Joint Electronic Device Engineering Council (JEDEC) Solid State Technology Association in their publication, DDR SDRAM Specification (JESD79), June 2000, a memory device must neither assert or deassert a strobe signal (DQS) 102 when it is not providing any data (DQ) 104 in response to a read command as illustrated by the timing diagram 100, as depicted in FIG. 1. However, the DQS signal 102 is driven to a known state, prior to being asserted, for a predetermined time interval referred to as a preamble 106. In addition, the DQS signal 102 is driven to a known state, following a final deassertion, for a predetermined period referred to as the postamble 108. In other words, when no read data DQ 104 is being transferred, the memory device should not drive the DQS signal 102 to a xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 voltage. This, however, causes a problem at the receiving device when the strobe line DQS 102 floats to the termination voltage, thereby causing the comparator output to become unstable due to the now essentially equal input voltages. This instability in turn will cause the unacceptable result that unintended bit values are captured by the latch from the data line DQ 102. In addition, the DQS signal 102 needs to be delayed, by a predetermined period 112, to a center of the data valid window 114, as illustrated by the delayed DQS signal 110.
Therefore, there remains a need to overcome one or more of the limitations in the above-described, existing art.